Sub-nanosecond pulse generator circuit

ABSTRACT

A transistorized sub-nanosecond pulse generator circuit having a pair of emitter coupled transistors in a monostable multivibrator configuration. By selecting an interstage capacitor, a collector load resistor, and a base bias or dividing resistor, in accordance with developed formulas, the operation of the transistorized pulse generator may effectively match the operation of conventional step-recovery-diode pulse generator circuits.

a United States Patent Bryden "SUB-NANOSECOND PULSE GENERATOR CIRCUIT[72] Inventor: Brian Richard Bryden, Kanata, On

tario, Canada [73] Assignee: Northern Electric Company Limited,

Montreal, Quebec, Canada 221 Filedi Sept. 23,1971

211 Appl.No.: 183,178

[52] U.S. Cl. ..307/273, 307/260, 307/290 [5 l] lnt. Cl. ..H03k 3/284,H03k 3/29 [58] Field of Search ..307/260, 265, 268, 269, 273, 7 307/290[56] 1 References Cited I V UNITED STATES PATENTS 3,205,372 9/1965 Pacl,Jr. ..307/290 X 1 Oct. 17, 1972 3,584,241 6/197] Nakamura ...307/290Primary Examiner-Stanley D. Miller, Jr. Attorney-John E. Mowle [57]ABSTRACT A transistorized sub-nanosecond pulse generator circuit havinga pair of emitter coupled transistors in a monostable multivibratorconfiguration. By selecting an interstage capacitor, a collector loadresistor, and a base bias or dividing resistor, in accordance withdeveloped formulas, the operation of the transistorized pulse generatormay effectively match the operation of conventional step-recovery-diodepulse generator circuits.

2 Claims, 2 Drawing Figures transistorized pulse generator circuit.

DESCRIPTION OF THE PRIOR ART In high speed pulse code modulationtransmission circuits, step recovery diodes are generally used in highspeed regenerators to generate sub-nanosecond width sampling pulseswhich are difficult to generate by other means. I

These step recovery diode, circuits have several disadvantages, chieflyamong these are: high excitation power requirements, non-linearimpedance presented to the driving source, poor stability of pulseheight and position with respect to temperature and drive signalvariations, and a general need to attenuate the output power fed to thefollowing stage.

A reference to the use of step recovery diodes may be found in thefollowing publication by I. Dorros; J .M. Sipress; and FD. Waldhauer,entitled An Experimental 224 Mb/s Digital Repeatered Line, Bell SystemsTechnical Journal, 45, September 1966, pp. 993-1 ,043. t I

SUMMARY OF THE INVENTION A transistorized circuit using two transistorsand several passive components, which does not exhibit many of thedisadvantages of step recovery diode pulse generators, has been found toperform the tasks performed by step recovery diode pulse generatorcircuits. This transistorized pulse generator circuit requires verylittle driving power, particularly as its input impedance is largelydependent on linear passive components connected across its input. Inaddition this transistorized generator operates over a wide range ofsignal inputs with little degredation of the output pulse shape orposition as said generator is sensitive primarily to the zero crossingsof the input voltage waveform. The transistorized generator circuit hasa temperature stability which is superior to that of conventional steprecovery diodecircuits, a circuit characteristic which is attributablein part to the use of emitter coupled .transistors. The transistorizedgenerator circuit has another unusual circuit characteristic in that itsoutput current pulse driving operation exceeds the quiescent currentflowing through an emitter resistor which procollector is also connectedto the base of the second vides the necessary common emitter coupling.Furthermore as the output level of the transistor pulse generator iscontrolled by passive components, the output level can be readilyadjusted to provide an output signal and circuit impedance compatiblewith following circuitry.

Thus in accordance with the present invention the transistorized pulsegenerator circuit comprises a first and a second transistor with theemitters of said transistors connected to a first source of potentialthrough a common emitter resistor. The base of the first transistor isconnected to an input terminal through an input coupling capacitor, andto a second source of potential through a base resistor. The collectorof the first transistor is connected through a collector load resistorto a third source of potential, and said transistor through aninterstage capacitor. The collector of the second transistor isconnected through an inductor to the third source-of potential, andthrough an output coupling capacitor to a load. The base of the secondtransistor is connected through a first dividing resistor to the thirdsource of potential and through a second dividing resistor to the secondsource of potential. i v t i The selection of the interstage capacitor,the collector load resistor, and the second dividing resistor isdetermined from the following equations:

where:

R is the resistance in ohms of the collector load resistor of the firsttransistor is the resistance in ohms of the second dividing resistor isthe low frequency capacitance in farads of the interstage capacitor isthe transistor header capacitance in farads measured between base andcollector L, is the series inductance in henries of the interstagecapacitor is the series capacitance in farads of the interstagecapacitor at the self resonant frequency f At low frequencies C, isapproximately equal to C is the current gain bandwidth figure of thesecond transistor (the frequency at which the short circuit collectorcurrent gain from base to collector equals unity) is the internal basespreading resistance in ohms of the second transistor when saidtransistor is represented by a hybrid 7r equivalent circuit is thecapacitance in farads between the internal base ,,r and the collector ofthe transistor when said transistor is represented by the hybrid 1requivalent circuit is the frequency at which the loop circuit gain fromthe collector of the first transistor through the base and emitter ofthe second transistor, through the emitter of the first transistor andback to the collector of the first transistor has a value of unity (loopA,B,C in FIG. 2) the self resonant frequency of the interstage capacitorC,.

fuss

BRIEF DESCRIPTION OF THE DRAWINGS An example embodiment of the inventionwill now be described with reference to the accompanying equivalentcircuit is used to represent the transistors illustrated in FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT transistor O to a third sourceof potential +V, while an inductor I. connects the collector of thesecond transistor to said third source of potential +V. The base of thefirst transistor Q is connected, to a second source of potential(ground) and through a capacitor C to an external driving circuit (theexternal driving circuit is not shown).

A load R illustrated schematically as a resistor in FIG. 1, is connectedto the second source of potential (ground) and is coupled to thecollector of the second transistor Q through a coupling capacitor C Toprovide for suitable biasing of the first Q and second Q transistors,the base of the first transistor 0 is connected through a first dividingresistor R to the third source of potential +V, and through a seconddividing resistor R to the second source of potential (ground).

In order to develop the equations which define the limits on the variouselements (R R C of the circuit illustrated schematically in FIG. 1, thefirst Q and second 0 transistors were represented by their hybrid 1requivalent circuits. The hybrid 'n' equivalent circuit used for thefirst Q and second Q transistors representations is illustrated in FIG.2. A similar hybrid 7r equivalent circuit may be found in the followingbook Introduction to Semiconductor Circuit Design by David J. Comer,Addison Wesley Publishing Company, pp. 174 et seq.

With reference to FIG. 2 it can be seen that the hybrid 1r equivalentcircuit comprises a resistive element n, which is commonly referred toas the internal base spreading resistance, a capacitive element C,,which represents the header capacitance of the transistor measuredbetween base b and collector c, and a capacitive element C whichrepresents the capacitance between the virtual or internal base b andthe collector c of the transistor. The other equivalent circuit elementsillustrated in FIG. 2 (C 3,, r,,' do not appear in the developedequations but may be found in the Comer reference.

In addition to the hybrid 12' parameters of the transistors Q and Qwhich are illustrated schematically in FIG. 2, the current gainbandwidth figure or f,, and the short circuit current gain or ,8 of thetransistors Q and 02 are taken into account in the design of a pulsegenerator in accordance with the present inventron.

As the hybrid 1r equivalent circuit, and as the various other transistorparameters referred to in the foregoing description are well known, nofurther explanation is believed necessary.

With reference to FIG. 1, the collector load resistor R the seconddividing resistor R and the interstage capacitor C are elements whichgreatly determine the upper frequency operating limit of the pulsegenerator. It has been found as one step in realizing the pulsegenerator, that the effective parallel resistance of the collector loadresistance R and the second dividing resistance R (written algebraicallyas R,]] R,,) can be related to the base spreading resistance r of thesecond transistor O by the following equation (Equation l Rasib'wiftecw14 2 1 In addition, as a further step in realizing pulse generatorperformance in accordance with the invention, the interstage capacitorshould have a minimum capacitance given by the following equationEquation Although there is apparently no theoretical upper limit on thecapacitance of the interstage capacitor C a practical upper limit isimposed by the series self resonant frequency f of the capacitor C Thisinterstage capacitor C should be chosen in accordance with the followingequation (Equation (3)):

In a typical circuit having a rise time of the orderof 200 picoseconds(and shown schematically in FIG. 1) the following component values wereused:

Q, and Q 2N5652 C, l0pf (picofarads) R 500 (ohms) R 1000 (ohms) L 5Snh(nanohenries) C .lul (microfarads) C, .luf (microfarads) R 4300. (ohms)R 509 (ohms) For a 2N5652 transistor Q the base spreading resistance rm,is approximately 20 ohms, the header capacitance C,, is approximately0.3pf, the capacitance C,, is approximately 0.4pf, and the current gainbandwidth figure f, is approximately 2.5 Ghz (Gigahertz).

Using the parameters for the 2N5652 transistor as outlined above, thelower and upper limits of R ll R can be calculated from Equation (1 (thelower limit is r or 209, while the upper limit approaches infinity). Theupper bound for R R in this example (with r,,,, =20Q) is not limited byEquation (1), (calculated resistance for R 1 1 R is infinity), but byother considerations such as biasing and transistor thermal stability.The resistance of R 11 R for the typical circuit which uses an R of ohmsand an R of 50 ohms is approximately 33 ohms.

The lower capacitance limit of the interstage coupling capacitor C ascalculated from Equation (2) yields a value of 0.8pf and as calculatedfrom Equation (5) yields a value of 1.06pf. The nominal value of C asused in a typical circuit is 10pf.

, ously defined. in

transistors by selecting R, R and C, as defined in the preceedingequations (Equations l) to (3) inclusive).

The base resistor R, is chosen to provide a suitable terminatingimpedance (approximately 500), for the driving circuit (not shown),while the input C, and outand the aforelisted values for a typicalcircuit using put C capacitors are chosen to present minimum im- 2N5 652transistors, f was calculated as 1.5Ghz.

The various terms of Equation (6) have been previone application anominal capacitance of l0pf and a self resonant frequency fags of 1.6Ghz was chosen for C,. As 1.6 Ghz l.5 Ghz Equation (3) is satisfied.

Although in the preferred embodiment and in the preceeding exampletransistors Q, and Q are shown as npn types, pnp type transistors withsuitable characteristics could be substituted provided the polarity ofthe first and third source are reversed. Additionally, the firsttransistor Q, and the second transistor 0, need not have the sametransistor code.

The operation of the preferred embodiment of the pulse generator when asuitable load resistor R, or

other terminating impedance is connected to the output will now bedescribed with reference to FIG. 1.

After the first dividing resistor R is adjusted or selected, such thatthe first transistor Q, is in its nonconducting state, an input signalwith a suitable waveform, is applied to the base of the first transistorQ, through the input capacitor C,,,. For simplicity of explanation theinput waveform will be assumed to be sinusoidal in form.

When the input signal waveform swings positive with respect to thesecond source of potential (ground), the

' first transistor 0, is turned ON and the second transistor 0 is turnedOFF such that the voltage at the collector of the second transistor Qrises to the value of the third source of potential +V. This positiveswing of the input signal waveform referred to above is the positivezero crossing of the sinusoidal input signal waveform. At the negativezero crossing of the sinusoidal input waveform, the second transistor Qquickly turns ON and a rapid current change flows from the second sourceof potential (ground), through the load resistor R the output capacitorC the second transistor 0,, and the emitter resistor R to the firstsource of potential -V. The presence of the conductor L, in series withthe collector of the second transistor Q and the third source ofpotential forces this rapid change of current to pass through the load RUnlike the voltage waveform which occurs at the collector of the secondtransistor 0, at the positive zero crossing of the input signalwaveform, the negative zero crossing of the input signal waveform isresponsible for a large sharp negative spike at the collector of thesecond transistor 0,. This large sharp negative spike has very steepsides (short rise and fall times) and is the desired output signal fromthe transistorized pulse generator circuit. The extraordinary behaviorof this circuit (its maximum operating frequency is approximately tentimes the maximum toggle rate of an equivalent multivibratorcircuit)results of the advantageous use of the non linear operation of thepedance to signal input current and. output load current within therange of operating frequencies.

What is claimed is:

l. A sub-nanosecond pulse generator circuit comprising:

a. first and second transistors, the emitters of said transistors beingconnected together;

b. an emitter resistor for connecting said emitters to a first source ofpotential;

0. an input coupling capacitor for connecting an input terminal to thebase of the first transistor;

d. a base resistor for connecting the base of the first transistor to asecond source of potential;

e. a collector load resistor forconnecting the collector of the firsttransistor to a third source of potential;

f. an inductor connecting the collector of the second transistor to thethird source of potential;

g. an output coupling capacitor for connecting the collector of thesecond transistor to a load;

h. a first dividing resistor for connecting the base of the secondtransistor to the third source of potentialand a second dividingresistor for connecting the base of the second transistor to the secondsource of potential;

i. an interstage capacitor connecting the collector of the firsttransistor to the base of the second transistor; wherein the resistanceof the parallel combination of the collector load resistor and thesecond dividing resistor is given by the following equation wherein theinterstage capacitor has a minimum capacitance given by the followingequation and wherein the interstage capacitor has a series self resonantfrequency given by the following equainterstage capacitor.

c. is the series capacitance in farads of the 2. The invention asdefined in claim 1 wherein'the renmmge "T l sistance of the parallelcombination of the collector frequencyf At low frequencies C, isapproximately equal to c,. load resistor and the second dividingresistor is given b f, is the current gain bandwidth figure of the th fllowing ation;

second transistor (the frequency at which the short circuit collectorcurrent gain r from base to collector equals unity) v r,,,,- is theinternal base spreading resistance in \Rl I 1 R3\ Tbb![41rft (2C C )]1(4) ohms of the second transistor when said transistor is represented bya hybrid 1r equivalent circuit CM is the capacitance in fmds between theand wherein the lnterstage capacitor has a mlnlmum internal base Q1 a dthe collector f the capacitance given by the following equationtransistor when said transistor is represented by the hybrid 1requivalent 3 circuit 0 f is the frequency at which the loop 9 r 2current gain from the collector of the first 41rR f (5 transistorthrough the base and emitter of V i t 4 V v the second transistor,through the emitter of the first transistor and back to the collector ofthe first transistor has a value of unity (loop A,B,C, in FIG. 2) firesthe self resonant frequency of the interstage capacitor C,,.

1. A sub-nanosecond pulse generator circuit comprising: a. first andsecond transistors, the emitters of said transistors being connectedtogether; b. an emitter resistor for connecting said emitters to a firstsource of potential; c. an input coupling capacitor for connecting aninput terminal to the base of the first transistor; d. a base resistorfor connecting the base of the first transistor to a second source ofpotential; e. a collector load resistor for connecting the collector ofthe first transistor to a third source of potential; f. an inductorconnecting the collector of the second transistor to the third source ofpotential; g. an output coupling capacitor for connecting the collectorof the second transistor to a load; h. a first dividing resistor forconnecting the base of the second transistor to the third source ofpotential and a second dividing resistor for connecting the base of thesecond transistor to the second source of potential; i. an interstagecapacitor connecting the collector of the first transistor to the baseof the second transistor; wherein the resistance of the parallelcombination of the collector load resistor and the second dividingresistor is given by the following equation wherein the interstagecapacitor has a minimum capacitance given by the following equation andwherein the interstage capacitor has a series self resonant frequencygiven by the following equation where: R1 is the resistance in ohms ofthe collector load resistor of the first transistor R3 is the resistancein ohms of the second dividing resistor C1 is the low frequencycapacitance in farads of the interstage capacitor Ch is the transistorheader capacitance in farads measured between base and collector Ls isthe series inductance in henries of the interstage capacitor. Cs is theseries capacitance in farads of the interstage capacitor at the selfresonant frequency fRES. At low frequencies Cs is approximately equal toC1. ft is the current gain bandwidth figure of the second transistor(the frequency at which the short circuit collector current gain frombase to collector equals unity) rbb is the inTernal base spreadingresistance in ohms of the second transistor when said transistor isrepresented by a hybrid pi equivalent circuit Cb c is the capacitance infarads between the internal base b and the collector of the transistorwhen said transistor is represented by the hybrid pi equivalent circuitfo is the frequency at which the loop current gain from the collector ofthe first transistor through the base and emitter of the secondtransistor, through the emitter of the first transistor and back to thecollector of the first transistor has a value of unity (loop A,B,C, inFIG. 2) fRES the self resonant frequency of the interstage capacitor Cs.2. The invention as defined in claim 1 wherein the resistance of theparallel combination of the collector load resistor and the seconddividing resistor is given by the following equation: and wherein theinterstage capacitor has a minimum capacitance given by the followingequation